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SanDisk Industrial Grade CompactFlash 5000 Product Manual
© 2007 SanDisk® Corporation 27 July 2007
PIO Data Transfers
Figure 10 defines the relationships between the interface signals for PIO data
transfers. For PIO Modes 3 and above the minimum value of t
0
is specified by
Word 68 in the IDENTIFY DEVICE parameter list. Table 22defines the
minimum value that will be placed in Word 68.
Figure 10: PIO Data Transfer to/from Device
Notes: 1) Device address consists of signals -CS0, -CS1 and -DA(2:0).
2) Data consists of DD(15:0).
The PIO data transfer parameters are defined in Table 22: PIO Data Transfer
to/from Device.
Note: SanDisk CompactFlash Memory cards do not assert an -IORDY signal.
Table 22: PIO Data Transfer to/from Device
PIO Timing Parameters Mode 0
(ns)
Mode 1
(ns)
Mode 2
(ns)
Mode 3
(ns)
Mode 4
(ns)
t0 a Cycle time (min.) 600 383 240 180 120
t1 Address valid to IORD-/IOWR- setup
(min.)
70 50 30 30 25
t2 a IORD-/IOWR- pulse width 16-bit (min.) 165 125 100 80 70
t2ia IORD-/IOWR- recovery time (min.) 70 25
t3 IOWR- data setup (min.) 60 45 30 30 20
t4 IOWR- data hold (min.) 30 20 15 10 10
t5 IORD- data setup (min.) 50 35 20 20 20
t6 IORD- data hold (min.) 5 5 5 5 5
t6a b IORD- data tri-state (max.) 30 30 30 30 30
t9 IORD-/IOWR- to address valid hold
(min.)
20 15 10 10 10
a. t0 is the minimum total cycle time, t2 is the minimum command active
time, and t2i is the minimum command recovery time or command
inactive time. The actual cycle time equals the sum of the actual command
active time and the actual command inactive time. The three timing
requirements of t0, t2, and t2i shall be met. The minimum total cycle time
requirements are greater than the sum of t2 and t2i. This means a host
- SanDisk Industrial Grade 1
- CompactFlash 5000 1
- Table of Contents 2
- List of Tables 5
- Introduction 8
- Features 9
- CompactFlash Standard 10
- PCMCIA Standard 10
- Related Documentation 10
- Functional Description 10
- Technology Independence 11
- Defect and Error Management 11
- Bad Block Management 12
- Automatic Sleep Mode 12
- Power Supply Requirements 12
- Wear Leveling 12
- Product Specifications 14
- System Power Requirements 15
- System Performance 15
- System Reliability 16
- Physical Specifications 16
- Regulatory Compliance 17
- Traceability 17
- Interface Description 18
- Electrical Description 20
- Table 10: Signal Description 21
- Electrical Specification 24
- Output Drive Characteristics 25
- Power Up/Down Timing 26
- Common Memory Read Timing 27
- Table 16 (continued) 28
- Memory Timing Diagrams 29
- I/O Read Timing Diagram 30
- True IDE Mode 32
- Card Configuration 35
- Attribute Memory Function 36
- Attribute Memory function 37
- Attribute Memory) 38
- 202h in Attribute Memory) 39
- Memory) 40
- I/O Transfer Function 41
- Configurations 43
- Memory Mapped Addressing 45
- True IDE Mode Addressing 46
- ATA Registers 46
- Read Only) 47
- Device Control Register 50
- Offset Fh) 50
- ATA Command Description 52
- Check Power Mode–98H, E5H 53
- Erase Sector(s)–C0H 54
- Format Track–50H 55
- Identify Device–ECH 55
- Idle–97H, E3H 63
- Idle Immediate–95H, E1H 63
- Read Buffer–E4H 64
- Read DMA Command–C8H, C9H 64
- Read Multiple–C4H 65
- Read Long Sector–22H, 23H 66
- Read Sector(s)–20H, 21H 66
- Recalibrate–1XH 67
- Request Sense–03H 67
- Seek–7XH 68
- Set Features–EFH 69
- Set Multiple Mode–C6H 70
- Set Sleep Mode–99H, E6H 70
- Standby–96H, E2H 71
- Standby Immediate–94H, E0H 71
- Translate Sector–87H 72
- Wear Level–F5H 72
- Write Buffer–E8H 73
- Write DMA Command–CAH, CBH 73
- Write Long Sector–32H, 33H 73
- Write Multiple Command–C5H 74
- Write Sector(s)–30H, 31H 75
- Write Verify Sector(s)–3CH 76
- Error Posting 77
- CIS Description 78
- I. Warranty Statement 95
- II. General Provisions 95
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