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SanDisk Industrial Grade CompactFlash 5000 Product Manual
© 2007 SanDisk® Corporation 68 July 2007
completion of the command e.g., each block has 4 sectors, a request for 8
sectors is issued and an error occurs on the third sector. The Sector Count
Register contains 6 and the address is that of the third sector.
5.1.29
Write Multiple without Erase–CDH
SanDisk does not recommend the use of this command in new designs but it is
supported as a normal Write Sectors command for backward compatibility.
Table 74: Write Multiple w/out Erase
5.1.30
Write Sector(s)–30H, 31H
This command writes from 1 to 256 sectors as specified in the Sector Count
Register. A sector count of zero requests 256 sectors. The transfer begins at
the sector specified in the Sector Number Register. When this command is
accepted, the card sets BSY, then sets DRQ and clears BSY, then waits for the
host to fill the sector buffer with the data to be written. No interrupt is
generated to start the first buffer fill operation. The host should not transmit
any data until it has cleared BSY.
For multiple sectors, after the first sector of data is in the buffer, BSY will be
set and DRQ will be cleared. After the next buffer is ready for data, BSY is
cleared, DRQ is set and an interrupt is generated. When the final sector of
data is transferred, BSY is set and DRQ is cleared. This state will be
maintained until the command is completed, at which time BSY is cleared and
an interrupt is generated.
If an error occurs during a write of more than one sector, writing terminates at
the sector in which the error occurs. The Command Block registers contain the
cylinder, head and sector number of the sector where the error occurred. The
host may then read the command block to determine what error occurred, and
on which sector.
Table 75: Write Sector(s)
- SanDisk Industrial Grade 1
- CompactFlash 5000 1
- Table of Contents 2
- List of Tables 5
- Introduction 8
- Features 9
- CompactFlash Standard 10
- PCMCIA Standard 10
- Related Documentation 10
- Functional Description 10
- Technology Independence 11
- Defect and Error Management 11
- Bad Block Management 12
- Automatic Sleep Mode 12
- Power Supply Requirements 12
- Wear Leveling 12
- Product Specifications 14
- System Power Requirements 15
- System Performance 15
- System Reliability 16
- Physical Specifications 16
- Regulatory Compliance 17
- Traceability 17
- Interface Description 18
- Electrical Description 20
- Table 10: Signal Description 21
- Electrical Specification 24
- Output Drive Characteristics 25
- Power Up/Down Timing 26
- Common Memory Read Timing 27
- Table 16 (continued) 28
- Memory Timing Diagrams 29
- I/O Read Timing Diagram 30
- True IDE Mode 32
- Card Configuration 35
- Attribute Memory Function 36
- Attribute Memory function 37
- Attribute Memory) 38
- 202h in Attribute Memory) 39
- Memory) 40
- I/O Transfer Function 41
- Configurations 43
- Memory Mapped Addressing 45
- True IDE Mode Addressing 46
- ATA Registers 46
- Read Only) 47
- Device Control Register 50
- Offset Fh) 50
- ATA Command Description 52
- Check Power Mode–98H, E5H 53
- Erase Sector(s)–C0H 54
- Format Track–50H 55
- Identify Device–ECH 55
- Idle–97H, E3H 63
- Idle Immediate–95H, E1H 63
- Read Buffer–E4H 64
- Read DMA Command–C8H, C9H 64
- Read Multiple–C4H 65
- Read Long Sector–22H, 23H 66
- Read Sector(s)–20H, 21H 66
- Recalibrate–1XH 67
- Request Sense–03H 67
- Seek–7XH 68
- Set Features–EFH 69
- Set Multiple Mode–C6H 70
- Set Sleep Mode–99H, E6H 70
- Standby–96H, E2H 71
- Standby Immediate–94H, E0H 71
- Translate Sector–87H 72
- Wear Level–F5H 72
- Write Buffer–E8H 73
- Write DMA Command–CAH, CBH 73
- Write Long Sector–32H, 33H 73
- Write Multiple Command–C5H 74
- Write Sector(s)–30H, 31H 75
- Write Verify Sector(s)–3CH 76
- Error Posting 77
- CIS Description 78
- I. Warranty Statement 95
- II. General Provisions 95
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